; F320_TimeCritical.asm generated from: F320_TimeCritical.c
; COMPILER INVOKED BY:
;        C:\Keil\C51\BIN\c51.exe F320_TimeCritical.c DB OE

$NOMOD51

NAME	F320_TIMECRITICAL

CCF2	BIT	0D8H.2
TB80	BIT	098H.3
CCF3	BIT	0D8H.3
P0	DATA	080H
SPIEN	BIT	0F8H.0
CCF4	BIT	0D8H.4
P1	DATA	090H
P2	DATA	0A0H
ADC0CF	DATA	0BCH
P3	DATA	0B0H
AC	BIT	0D0H.6
EIE1	DATA	0E6H
EA	BIT	0A8H.7
MCE0	BIT	098H.5
USB0XCN	DATA	0D7H
PSCTL	DATA	08FH
CF	BIT	0D8H.7
IT01CF	DATA	0E4H
ADC0CN	DATA	0E8H
P0MDOUT	DATA	0A4H
P1MDOUT	DATA	0A5H
TMR2RLH	DATA	0CBH
IE	DATA	0A8H
P2MDOUT	DATA	0A6H
P3MDOUT	DATA	0A7H
TMR3RLH	DATA	093H
EIP1	DATA	0F6H
TXBMT	BIT	0F8H.1
PCA0CPH0	DATA	0FCH
TMR2RLL	DATA	0CAH
PCA0CPH1	DATA	0EAH
TMR3RLL	DATA	092H
PCA0CPH2	DATA	0ECH
CR	BIT	0D8H.6
TF2H	BIT	0C8H.7
T2SPLIT	BIT	0C8H.3
PCA0CPH3	DATA	0EEH
REN0	BIT	098H.4
PCA0CPH4	DATA	0FEH
PCA0CPL0	DATA	0FBH
PCA0CPL1	DATA	0E9H
PCA0CPM0	DATA	0DAH
PCA0MD	DATA	0D9H
PCA0CN	DATA	0D8H
PCA0CPL2	DATA	0EBH
PCA0CPM1	DATA	0DBH
TF2L	BIT	0C8H.6
PCA0CPL3	DATA	0EDH
PCA0CPM2	DATA	0DCH
IP	DATA	0B8H
ARBLOST	BIT	0C0H.2
PCA0CPL4	DATA	0FDH
PCA0CPM3	DATA	0DDH
PCA0CPM4	DATA	0DEH
TXBSY	BIT	0F8H.3
CY	BIT	0D0H.7
SI	BIT	0C0H.0
XBR0	DATA	0E1H
SMB0CF	DATA	0C1H
XBR1	DATA	0E2H
EMI0CN	DATA	0AAH
REF0CN	DATA	0D1H
REG0CN	DATA	0C9H
AD0INT	BIT	0E8H.5
SP	DATA	081H
OV	BIT	0D0H.2
SMB0CN	DATA	0C0H
TMR2	DATA	0CCH
MODF	BIT	0F8H.5
S0MODE	BIT	098H.7
VDM0CN	DATA	0FFH
P0MDIN	DATA	0F1H
CPT0MD	DATA	09DH
CPT0CN	DATA	09BH
P1MDIN	DATA	0F2H
CPT1MD	DATA	09CH
CPT1CN	DATA	09AH
P2MDIN	DATA	0F3H
TF2LEN	BIT	0C8H.5
P3MDIN	DATA	0F4H
SPI0CN	DATA	0F8H
PCON	DATA	087H
SPIF	BIT	0F8H.7
TMOD	DATA	089H
TCON	DATA	088H
WCOL	BIT	0F8H.6
TMR2CN	DATA	0C8H
MOSI	BIT	090H.6
MISO	BIT	090H.5
P0SKIP	DATA	0D4H
TMR3CN	DATA	091H
T2XCLK	BIT	0C8H.0
P1SKIP	DATA	0D5H
P2SKIP	DATA	0D6H
IE0	BIT	088H.1
SPICFG	DATA	0A1H
CPT0MX	DATA	09FH
IE1	BIT	088H.3
OSCICL	DATA	0B3H
CPT1MX	DATA	09EH
CLKSEL	DATA	0A9H
B	DATA	0F0H
ADC0H	DATA	0BEH
OSCICN	DATA	0B2H
TMR2RL	DATA	0CAH
ADC0L	DATA	0BDH
ACC	DATA	0E0H
SPIDAT	DATA	0A3H
ES0	BIT	0A8H.4
AD0EN	BIT	0E8H.7
ET0	BIT	0A8H.1
ET1	BIT	0A8H.3
TF0	BIT	088H.5
CLKMUL	DATA	0B9H
ET2	BIT	0A8H.5
RI0	BIT	098H.0
TF1	BIT	088H.7
TH0	DATA	08CH
EX0	BIT	0A8H.0
TI0	BIT	098H.1
IT0	BIT	088H.0
PCA0H	DATA	0FAH
TH1	DATA	08DH
MASTER	BIT	0C0H.7
EX1	BIT	0A8H.2
IT1	BIT	088H.2
SPICKR	DATA	0A2H
P	BIT	0D0H.0
ACK	BIT	0C0H.1
OSCXCN	DATA	0B1H
TL0	DATA	08AH
PCA0L	DATA	0F9H
TL1	DATA	08BH
TXMODE	BIT	0C0H.6
PS0	BIT	0B8H.4
PT0	BIT	0B8H.1
RS0	BIT	0D0H.3
PT1	BIT	0B8H.3
RADIO_RESET	BIT	090H.2
RS1	BIT	0D0H.4
PT2	BIT	0B8H.5
TR0	BIT	088H.4
AD0TM	BIT	0E8H.6
TR1	BIT	088H.6
TR2	BIT	0C8H.2
PX0	BIT	0B8H.0
PX1	BIT	0B8H.2
SLVSEL	BIT	0F8H.2
DPH	DATA	083H
ADC0GTH	DATA	0C4H
DPL	DATA	082H
SCK	BIT	090H.4
ADC0GTL	DATA	0C3H
SBUF0	DATA	099H
ADC0LTH	DATA	0C6H
RSTSRC	DATA	0EFH
SCON0	DATA	098H
AMX0N	DATA	0BAH
ADC0LTL	DATA	0C5H
AMX0P	DATA	0BBH
STA	BIT	0C0H.5
SMB0DAT	DATA	0C2H
TMR2H	DATA	0CDH
TMR3H	DATA	095H
CKCON	DATA	08EH
RXOVRN	BIT	0F8H.4
TMR2L	DATA	0CCH
ACKRQ	BIT	0C0H.3
USB0ADR	DATA	096H
TMR3L	DATA	094H
F0	BIT	0D0H.5
FLSCL	DATA	0B6H
USB0DAT	DATA	097H
AD0CM0	BIT	0E8H.0
F1	BIT	0D0H.1
STO	BIT	0C0H.4
AD0CM1	BIT	0E8H.1
AD0CM2	BIT	0E8H.2
AD0WINT	BIT	0E8H.3
AD0BUSY	BIT	0E8H.4
PSW	DATA	0D0H
CCF0	BIT	0D8H.0
RB80	BIT	098H.2
FLKEY	DATA	0B7H
SEN_bar	BIT	090H.3
CCF1	BIT	0D8H.1
?PR?Timer2_ISR?F320_TIMECRITICAL         SEGMENT CODE 
?PR?Handle_In3?F320_TIMECRITICAL         SEGMENT CODE 
?PR?Turn_On_Stream?F320_TIMECRITICAL     SEGMENT CODE 
?PR?Turn_Off_Stream?F320_TIMECRITICAL    SEGMENT CODE 
	EXTRN	CODE (In1_StateMachine)
	EXTRN	DATA (Next_LED_Mode)
	EXTRN	CODE (_FIFO_Purge)
	EXTRN	CODE (LED_StateMachine)
	PUBLIC	AudioSamples
	PUBLIC	Turn_Off_Stream
	PUBLIC	Turn_On_Stream
	PUBLIC	Handle_In3
	PUBLIC	Timer2_ISR

	XSEG  AT  00H
   AudioSamples:   DS   1024
; //-----------------------------------------------------------------------------
; // F320_TimeCritical.c
; //-----------------------------------------------------------------------------
; // Copyright 2006 Silicon Laboratories, Inc.
; // http://www.silabs.com
; //
; // Program Description:
; //
; // This module contains mixed C and assembly for time critical code portions.
; // When it is compiled, it updates F320_TimeCritical.asm, which is included in
; // the normal project build.  The code in this module is hand optimized to meet
; // timing requirements for this specific application.  Modifications to this
; // module should be kept to a minimum, or avoided entirely.
; //
; // FID:            32X000000
; // Target:         C8051F320
; // Tool chain:     KEIL C51 7.0.0.1 / KEIL A51 7.0.0.1
; //                 Silicon Laboratories IDE version 2.3
; // Command Line:   See Readme.txt
; // Project Name:   F320_FM_Radio
; //
; // Release 1.1
; //    -No changes made to this module (DM)
; //    -16 JAN 2006
; //
; // Release 1.0
; //    -Initial Revision (DM)
; //    -05 AUG 2005
; //
; //
; //-----------------------------------------------------------------------------
; // Preprocessor Directives
; //-----------------------------------------------------------------------------
; 
; #pragma SRC(F320_TimeCritical.asm)
; 
; //-----------------------------------------------------------------------------
; // Includes
; //-----------------------------------------------------------------------------
; 
; #include "c8051f320.h"                 // SFR declarations
; #include "F320_FM_RadioMain.h"         // Main project header
; #include "F320_USB_Register.h"         // USB core register header
; #include "F320_USB_Common.h"           // USB protocol header
; #include "F320_USB_Descriptor.h"       // USB descriptor definitions
; #include "F320_LED_Control.h"          // LED control header
; 
; //-----------------------------------------------------------------------------
; // Variable Declaration
; //-----------------------------------------------------------------------------
; 
; // Placeholder for audio samples
; xdata BYTE AudioSamples[1024] _at_ 0x0000;
; 
; //-----------------------------------------------------------------------------
; // Timer2_ISR
; //
; // Return Value : None
; // Parameters   : None
; //
; // Switches the ADC multiplexor value right after a conversion is started.
; // This switches between the right and left audio channels.  This routine really
; // uses bank 0, which is otherwise unused after initialization routines finish
; // in the main program thread.  This interrupt is high priority, and uses
; // EMI0CN and R1 to access xdata software buffer, while the low priority USB
; // ISR routine Handle_In3 uses the data pointer to access the same buffer.
; // Using this method for buffer access reduces the amount of required context
; // saving/restoring between the two ISRs.  The audio samples are four bytes,
; // spread across the four 256 byte xdata pages.  For instance, if byte 0 is at
; // address 0, then byte 1 is at address 256, byte 2 is at address 512, and
; // byte 3 is at address 768.
; //
; //-----------------------------------------------------------------------------
CSEG	AT	0002BH
	LJMP	Timer2_ISR

; void Timer2_ISR (void) interrupt 5

	RSEG  ?PR?Timer2_ISR?F320_TIMECRITICAL
	USING	0
Timer2_ISR:
	PUSH 	ACC
			; SOURCE LINE # 74
; {
;    AMX0P ^= 0x01;                      // Switch between left and right channel
			; SOURCE LINE # 76
	XRL  	AMX0P,#01H
; 
;    #pragma asm
;    USING 0;                            // Really using register bank 0
	  USING 0;                             
; 
	  
; 	PUSH 	 PSW;
	  PUSH 	 PSW;
; 	MOV    PSW,#00H;
	  MOV    PSW,#00H;
;    #pragma endasm
; 
;    if (!(AMX0P & 0x01))                // Determine which channel is selected
			; SOURCE LINE # 85
	MOV  	A,AMX0P
	JB   	ACC.0,?C0001
;    {
			; SOURCE LINE # 86
;       #pragma asm
;       MOV   EMI0CN, #00H;              // Set EMI0CN to target xram page 0
	  MOV   EMI0CN, #00H;               
; 
	  
;       MOV   A,ADC0L;
	  MOV   A,ADC0L;
;       MOVX  @R1,A;                     // Move left sample low byte to buffer
	  MOVX  @R1,A;                      
; 
	  
;       INC   EMI0CN;                    // EMI0CN now targets xram page 1
	  INC   EMI0CN;                     
; 
	  
;       MOV   A,ADC0H;
	  MOV   A,ADC0H;
;       XRL   A,#80H;                    // Convert to signed two's-complement
	  XRL   A,#80H;                     
;       MOVX  @R1,A;                     // Move left sample high byte to buffer
	  MOVX  @R1,A;                      
;       #pragma endasm
;    }
			; SOURCE LINE # 99
	SJMP 	?C0002
?C0001:
;    else
;    {
			; SOURCE LINE # 101
;       #pragma asm
;       INC   EMI0CN;                    // EMI0CN now targets xram page 2
	  INC   EMI0CN;                     
; 
	  
;       MOV   A,ADC0L;
	  MOV   A,ADC0L;
;       MOVX  @R1,A;                     // Move right sample low byte to buffer
	  MOVX  @R1,A;                      
; 
	  
;       INC   EMI0CN;                    // EMI0CN now targets xram page 3
	  INC   EMI0CN;                     
; 
	  
;       MOV   A,ADC0H;
	  MOV   A,ADC0H;
;       XRL   A,#80H;                    // Convert to signed two's-complement
	  XRL   A,#80H;                     
;       MOVX  @R1,A;                     // Move right sample high byte to buffer
	  MOVX  @R1,A;                      
; 
	  
;       INC   R1;                        // Increment write pointer
	  INC   R1;                         
; 
	  
;       MOV   A, R1;                     // Check to see if buffer is full
	  MOV   A, R1;                      
;       XRL   A, R2;                     // by checking if R1 = R2
	  XRL   A, R2;                      
;       JNZ   BUFFER_NOT_FULL;
	  JNZ   BUFFER_NOT_FULL;
;          DEC   R1;                     // If so, throw away this sample
	  DEC   R1;                      
;       BUFFER_NOT_FULL:
	  BUFFER_NOT_FULL:
;       #pragma endasm
;    }
			; SOURCE LINE # 122
?C0002:
; 
;    TF2H = 0;                           // Clear Timer2 interrupt flag
			; SOURCE LINE # 124
	CLR  	TF2H
; 
;    #pragma asm
; 	POP   PSW;
	  POP   PSW;
;    #pragma endasm
; }
			; SOURCE LINE # 129
	POP  	ACC
	RETI 	
; END OF Timer2_ISR

; 
; //-----------------------------------------------------------------------------
; // Handle_In3
; //-----------------------------------------------------------------------------
; //
; // Return Value : None
; // Parameters   : None
; //
; // This routine write up to 97 samples per millisecond from the software buffer
; // to the USB fifo for endpoint 3.  The register usage is as follows:
; //
; // Write Pointer is R1
; // Read Pointer is R2
; // Number of bytes to write is R3
; // Number of samples to write is stored in accumulator
; //
; // Each sample is 4 bytes and each byte of the sample is stored at the same
; // 8-bit address on separate XRAM pages.  See Timer2_ISR comments for more
; // detailed description.
; //
; //-----------------------------------------------------------------------------
; void Handle_In3 (void)

	RSEG  ?PR?Handle_In3?F320_TIMECRITICAL
Handle_In3:
	USING	0
			; SOURCE LINE # 151
; {
			; SOURCE LINE # 152
?C0004:
;    while (USB0ADR & 0x80);             // Wait for BUSY->'0'               
			; SOURCE LINE # 153
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0004
?C0005:
;    USB0ADR = (FIFO_EP3);               // Set address
			; SOURCE LINE # 154
	MOV  	USB0ADR,#023H
; 
;    #pragma asm
;    USING 0;                            // Really using register bank 0
	  USING 0;                             
; 
	  
;    PUSH  PSW;
	  PUSH  PSW;
;    MOV   PSW,#00H;
	  MOV   PSW,#00H;
; 
	  
;    CLR   EA;                           // Turn off interrupts
	  CLR   EA;                            
;    CLR   EA;
	  CLR   EA;
; 
	  
;    CLR  	C;                            // Calculate number of samples in buffer
	  CLR  	C;                             
;    MOV  	A,R1;                         // with interrupts off
	  MOV  	A,R1;                          
;    SUBB 	A,R2;
	  SUBB 	A,R2;
;    MOV  	R3,A;
	  MOV  	R3,A;
; 
	  
;    SETB  EA;                           // Turn on interrupts
	  SETB  EA;                            
; 
	  
;    MOV  	A,R3;                         // Only write up to 97 samples
	  MOV  	A,R3;                          
;    SETB 	C;
	  SETB 	C;
;    SUBB 	A,#061H;
	  SUBB 	A,#061H;
;    JC   	ENOUGH_FIFO_SPACE;
	  JC   	ENOUGH_FIFO_SPACE;
;          MOV  	R3,#061H;
	  MOV  	R3,#061H;
;    ENOUGH_FIFO_SPACE:
	  ENOUGH_FIFO_SPACE:
; 
	  
;    BEGIN_WRITE_LOOP:
	  BEGIN_WRITE_LOOP:
;       MOV   DPL, R2;                   // Datapointer low byte = write pointer
	  MOV   DPL, R2;                    
;       MOV   DPH, #00H;                 // Datapointer high byte = xram page 0
	  MOV   DPH, #00H;                  
;   
	  
;       POLL1:
	  POLL1:
;          MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;          JB ACC.7,POLL1;               // Wait for access to USB SIE
	  JB ACC.7,POLL1;                
; 
	  
;       MOVX  A,@DPTR;                   // Move left sample low byte
	  MOVX  A,@DPTR;                    
;       MOV   USB0DAT, A;                // to USB FIFO
	  MOV   USB0DAT, A;                 
; 
	  
;       INC   DPH;                       // Datapointer high byte = xram page 1
	  INC   DPH;                        
; 
	  
;       POLL2:
	  POLL2:
;          MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;          JB ACC.7,POLL2;               // Wait for access to USB SIE
	  JB ACC.7,POLL2;                
;    
	  
;       MOVX  A,@DPTR;                   // Move left sample high byte
	  MOVX  A,@DPTR;                    
;       MOV   USB0DAT, A;                // to USB FIFO
	  MOV   USB0DAT, A;                 
; 
	  
;       INC   DPH;                       // Datapointer high byte = xram page 2
	  INC   DPH;                        
; 
	  
;       POLL3:
	  POLL3:
;          MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;          JB ACC.7,POLL3;               // Wait for access to USB SIE
	  JB ACC.7,POLL3;                
;    
	  
;       MOVX  A,@DPTR;                   // Move right sample low byte
	  MOVX  A,@DPTR;                    
;       MOV   USB0DAT, A;                // to USB FIFO
	  MOV   USB0DAT, A;                 
; 
	  
;       INC   DPH;                       // Datapointer high byte = xram page 3
	  INC   DPH;                        
; 
	  
;       POLL4:
	  POLL4:
;          MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;          JB ACC.7,POLL4;               // Wait for access to USB SIE
	  JB ACC.7,POLL4;                
;    
	  
;       MOVX  A,@DPTR;                   // Move right sample high byte
	  MOVX  A,@DPTR;                    
;       MOV   USB0DAT, A;                // to USB FIFO
	  MOV   USB0DAT, A;                 
; 
	  
;       INC   R2;                        // Increment write pointer
	  INC   R2;                         
; 
	  
;       DJNZ  R3, BEGIN_WRITE_LOOP;      // Loop if there is still data to write
	  DJNZ  R3, BEGIN_WRITE_LOOP;       
;    END_WRITE_LOOP:
	  END_WRITE_LOOP:
; 
	  
;    POP   PSW;
	  POP   PSW;
;    #pragma endasm
; 
;    // Set rbInINPRDY to send data to host
;    POLL_WRITE_BYTE (EINCSR1, rbInINPRDY);
			; SOURCE LINE # 226
?C0006:
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0006
?C0007:
	MOV  	USB0ADR,#011H
	MOV  	USB0DAT,#01H
; 
;    LED_StateMachine ();                // Update LED state
			; SOURCE LINE # 228
	LCALL	LED_StateMachine
;    In1_StateMachine ();
			; SOURCE LINE # 229
	LJMP 	In1_StateMachine
; END OF Handle_In3

; }
; 
; //-----------------------------------------------------------------------------
; // Turn_On_Stream
; //-----------------------------------------------------------------------------
; //
; // Return Value : None
; // Parameters   : None
; //
; // This function purges the USB FIFO, and puts then puts the device's Vendor
; // and product ID on the USB FIFO.  This ensures that a transmit complete
; // interrupt will be generated while the F320 buffers the first millisecond of
; // samples.  By putting this identification in the data stream, the host can
; // be sure it is communicating with the correct USB audio device.
; //
; //-----------------------------------------------------------------------------
; void Turn_On_Stream (void) using USB_REGISTER_BANK

	RSEG  ?PR?Turn_On_Stream?F320_TIMECRITICAL
Turn_On_Stream:
	USING	1
	PUSH 	PSW
	MOV  	PSW,#08H
			; SOURCE LINE # 246
; {
;     FIFO_Purge (3);                    // Index is set to 3 in this call
			; SOURCE LINE # 248
	MOV  	R7,#03H
	LCALL	_FIFO_Purge
; 
;    #pragma asm
; 
	  
;    USING 0;                            // Really using register bank 0
	  USING 0;                             
; 
	  
;    PUSH  PSW;
	  PUSH  PSW;
;    MOV   PSW,#00H;
	  MOV   PSW,#00H;
;    
	  
;    MOV   R1,#00H;                      // Reset read and write pointers
	  MOV   R1,#00H;                       
;    MOV   R2,#00H;
	  MOV   R2,#00H;
; 
	  
;    POLL10:
	  POLL10:
;       MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;       JB ACC.7,POLL10;                 // Wait for access to USB SIE
	  JB ACC.7,POLL10;                  
; 	MOV   USB0ADR,#023H;                // Configure to write endpoint 3 FIFO
	  MOV   USB0ADR,#023H;                 
; 
	  
;    POLL11:
	  POLL11:
;       MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;       JB ACC.7,POLL11;                 // Wait for access to USB SIE
	  JB ACC.7,POLL11;                  
;    MOV   A, #VID_LSB;
	  MOV   A, #0xC4;
;    MOV   USB0DAT, A;                   // Write vendor ID low byte
	  MOV   USB0DAT, A;                    
; 
	  
;    POLL12:
	  POLL12:
;       MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;       JB ACC.7,POLL12;                 // Wait for access to USB SIE
	  JB ACC.7,POLL12;                  
;    MOV   A, #VID_MSB;
	  MOV   A, #0x10;
;    MOV   USB0DAT, A;                   // Write vendor ID high byte
	  MOV   USB0DAT, A;                    
; 
	  
;    POLL13:
	  POLL13:
;       MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;       JB ACC.7,POLL13;                 // Wait for access to USB SIE
	  JB ACC.7,POLL13;                  
;    MOV   A, #PID_LSB;
	  MOV   A, #0x8A;
;    MOV   USB0DAT, A;                   // Write product ID low byte
	  MOV   USB0DAT, A;                    
; 
	  
;    POLL14:
	  POLL14:
;       MOV   A,USB0ADR;
	  MOV   A,USB0ADR;
;       JB ACC.7,POLL14;                 // Wait for access to USB SIE
	  JB ACC.7,POLL14;                  
;    MOV   A, #PID_MSB;
	  MOV   A, #0x81;
;    MOV   USB0DAT, A;                   // Write product ID high byte
	  MOV   USB0DAT, A;                    
; 
	  
;    POP   PSW;
	  POP   PSW;
; 
	  
;    #pragma endasm
; 
;    // Set rbInINPRDY to send data to host
;    POLL_WRITE_BYTE (EINCSR1, rbInINPRDY);
			; SOURCE LINE # 294
?C0009:
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0009
?C0010:
	MOV  	USB0ADR,#011H
	MOV  	USB0DAT,#01H
;                
;    AMX0P = 0x09;                       // Positive input starts as P2.1, left
			; SOURCE LINE # 296
	MOV  	AMX0P,#09H
;    ADC0L = 0x00;                       // Write zero values to ADC
			; SOURCE LINE # 297
	CLR  	A
	MOV  	ADC0L,A
;    ADC0H = 0x80;
			; SOURCE LINE # 298
	MOV  	ADC0H,#080H
; 
;    // Enable Reset, and Suspend interrupts; Disable SOF interrupts
;    POLL_WRITE_BYTE (CMIE, rbRSTINTE | rbSUSINTE);
			; SOURCE LINE # 301
?C0011:
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0011
?C0012:
	MOV  	USB0ADR,#0BH
	MOV  	USB0DAT,#05H
; 
;    POLL_WRITE_BYTE (IN1IE,  0x09);     // Enable Endpoint 0 and 3 in interrupts
			; SOURCE LINE # 303
?C0013:
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0013
?C0014:
	MOV  	USB0ADR,#07H
	MOV  	USB0DAT,#09H
; 
;    Next_LED_Mode = ALL_COLOR_LED;      // Set next LED state
			; SOURCE LINE # 305
	MOV  	Next_LED_Mode,#01H
; 
;    TR2 = ON;                           // Start timer 2
			; SOURCE LINE # 307
	SETB 	TR2
; }
			; SOURCE LINE # 308
	POP  	PSW
	RET  	
; END OF Turn_On_Stream

; 
; //-----------------------------------------------------------------------------
; // Turn_Off_Stream
; //-----------------------------------------------------------------------------
; //
; // Return Value : None
; // Parameters   : None
; //
; // This routine stops is called when the device should stop sampling audio and
; // be able to accept control commands from the host.
; //
; //-----------------------------------------------------------------------------
; void Turn_Off_Stream (void) using USB_REGISTER_BANK

	RSEG  ?PR?Turn_Off_Stream?F320_TIMECRITICAL
Turn_Off_Stream:
	USING	1
	PUSH 	PSW
	MOV  	PSW,#08H
			; SOURCE LINE # 321
; {
;    TR2 = OFF;
			; SOURCE LINE # 323
	CLR  	TR2
; 
;    POLL_WRITE_BYTE (IN1IE,  0x01);     // Enable Endpoint 0 interrupts only
			; SOURCE LINE # 325
?C0016:
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0016
?C0017:
	MOV  	USB0ADR,#07H
	MOV  	USB0DAT,#01H
; 
;    FIFO_Purge (3);                     // Index is set to 3 in this call
			; SOURCE LINE # 327
	MOV  	R7,#03H
	LCALL	_FIFO_Purge
; 
;    Next_LED_Mode = BLINK_GREEN_LED;    // Set next LED state
			; SOURCE LINE # 329
	MOV  	Next_LED_Mode,#02H
; 
;    // Enable SOF, Reset, and Suspend interrupt
;    POLL_WRITE_BYTE (CMIE, rbSOFE | rbRSTINTE | rbSUSINTE);
			; SOURCE LINE # 332
?C0018:
	MOV  	A,USB0ADR
	JB   	ACC.7,?C0018
?C0019:
	MOV  	USB0ADR,#0BH
	MOV  	USB0DAT,#0DH
;    
; }
			; SOURCE LINE # 334
	POP  	PSW
	RET  	
; END OF Turn_Off_Stream

	END
